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17 lines
274 B
Plaintext
17 lines
274 B
Plaintext
read_verilog <<EOT
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module top(input a, output y);
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assign y = !a;
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endmodule
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EOT
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prep -top top
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write_verilog write_gzip.v.gz
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design -reset
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! rm -f write_gzip.v
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! gunzip write_gzip.v.gz
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read_verilog write_gzip.v
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! rm -f write_gzip.v
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hierarchy -top top
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select -assert-any top
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