3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 09:04:08 +00:00
yosys/tests/various/stat.ys
2025-03-19 13:43:44 +01:00

15 lines
344 B
Plaintext

read_rtlil << EOF
module \top
wire input 1 \A
wire output 2 \Y
cell \sg13g2_and2_1 \sub
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
EOF
logger -expect log "Chip area for module '\\top': 9.072000" 1
logger -expect-no-warnings
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz