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yosys/tests/various/port_sign_extend.ys
Zachary Snow 4b2f977331 genrtlil: fix signed port connection codegen failures
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00

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read_verilog -nomem2reg port_sign_extend.v
hierarchy
flatten
proc
memory
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
read_verilog -nomem2reg port_sign_extend.v
flatten
proc
memory
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
read_verilog -nomem2reg port_sign_extend.v
hierarchy
proc
memory
equiv_make ref act equiv
prep -flatten -top equiv
equiv_induct
equiv_status -assert