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Zachary Snow 8de2e863af verilog: support recursive functions using ternary expressions

This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.

2021-02-12 14:43:42 -05:00

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 read_verilog fib_tern.v
 hierarchy
 proc
 equiv_make gold gate equiv
 equiv_simple
 equiv_status -assert