mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 09:04:08 +00:00
10 lines
186 B
Plaintext
10 lines
186 B
Plaintext
read_verilog <<EOT
|
|
module top(input i, output o);
|
|
assign o = i;
|
|
endmodule
|
|
EOT
|
|
design -stash foo
|
|
design -delete foo
|
|
logger -expect error "No saved design 'foo' found!" 1
|
|
design -load foo
|