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30 lines
417 B
Plaintext
30 lines
417 B
Plaintext
read_verilog <<EOF
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module gcd(I, D);
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output [2:0] I;
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input [3:0] D;
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assign I = D[0]+D[1]+D[2]+D[3];
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endmodule
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EOF
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design -save input
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prep
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design -stash gold
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design -load input
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synth -top gcd -flatten
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extract_fa -v
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design -stash gate
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design -copy-from gold -as gold gcd
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design -copy-from gate -as gate gcd
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-all miter
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