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22 lines
393 B
Verilog
22 lines
393 B
Verilog
function [7:0] do_add;
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input [7:0] inp_a;
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input [7:0] inp_b;
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do_add = inp_a + inp_b;
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endfunction
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module foo(clk, rst, inp_a, inp_b, out);
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input wire clk;
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input wire rst;
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input wire [7:0] inp_a;
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input wire [7:0] inp_b;
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output reg [7:0] out;
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always @(posedge clk)
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if (rst) out <= 0;
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else out <= do_add (* combinational_adder *) (inp_a, inp_b);
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endmodule
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