mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
9 lines
75 B
Verilog
9 lines
75 B
Verilog
module top;
|
|
sub s0();
|
|
foo f0();
|
|
endmodule
|
|
|
|
module foo;
|
|
sub s0();
|
|
endmodule
|