mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
12 lines
179 B
Systemverilog
12 lines
179 B
Systemverilog
module local_loop_top(out);
|
|
output integer out;
|
|
initial begin
|
|
integer i;
|
|
for (i = 0; i < 5; i = i + 1)
|
|
if (i == 0)
|
|
out = 1;
|
|
else
|
|
out += 2 ** i;
|
|
end
|
|
endmodule
|