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https://github.com/YosysHQ/yosys
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76c615b2ae
Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
21 lines
681 B
Plaintext
21 lines
681 B
Plaintext
# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
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autoidx 2
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attribute \architecture "Behavioral"
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attribute \library "work"
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attribute \hdlname "vector_assign"
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attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
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module \vector_assign
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attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
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wire width 4 input 2 \a
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attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
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wire width 4 output 1 \b
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attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
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cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
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parameter \A_SIGNED 0
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parameter \A_WIDTH 4
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parameter \Y_WIDTH 4
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connect \A \a
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connect \Y \b
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end
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end
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