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https://github.com/YosysHQ/yosys
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76c615b2ae
Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
29 lines
418 B
Plaintext
29 lines
418 B
Plaintext
$date
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Fri Sep 27 11:58:46 2024
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$end
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$version
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GHDL v0
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$end
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$timescale
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1 fs
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$end
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$scope module standard $end
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$upscope $end
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$scope module std_logic_1164 $end
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$upscope $end
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$scope module tb $end
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$var reg 4 ! a [3:0] $end
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$var reg 4 " b [3:0] $end
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$scope module uut $end
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$var reg 4 # a [3:0] $end
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$var reg 4 $ b [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b0001 !
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b0001 "
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b0001 #
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b0001 $
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#10000000
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