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yosys/tests/sim/simple_assign.vcd
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-02 12:08:48 +02:00

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$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2