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yosys/tests/sim/sim_sdff.ys
Miodrag Milanovic 271ac28b41 Added test cases
2022-02-16 13:27:59 +01:00

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read_verilog sdff.v
proc
opt_dff
stat
select -assert-count 1 t:$sdff
sim -clock clk -r tb_sdff.fst -scope tb_sdff.uut -sim-cmp sdff