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23 lines
453 B
Verilog
23 lines
453 B
Verilog
module opt_share_test(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input sel,
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output reg [47:0] res,
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);
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wire [15:0] add_res = a+b;
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wire [15:0] sub_res = a-b;
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wire [31: 0] cat1 = {add_res, c+d};
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wire [31: 0] cat2 = {sub_res, c-d};
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always @* begin
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case(sel)
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0: res = {cat1, add_res};
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1: res = {cat2, add_res};
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endcase
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end
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endmodule
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