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https://github.com/YosysHQ/yosys
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7f033d3c1f
Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
20 lines
294 B
Plaintext
20 lines
294 B
Plaintext
ram distributed \LUT_MULTI {
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abits 4;
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width 2;
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init any;
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port arsw "RW" {
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clock posedge;
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}
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ifdef PORTS_QUAD {
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option "PORTS" "QUAD" {
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port ar "R0" "R1" "R2" {
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}
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}
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} else ifdef PORTS_OCT {
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option "PORTS" "OCT" {
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port ar "R0" "R1" "R2" "R3" "R4" "R5" "R6" {
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}
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}
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}
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}
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