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23 lines
317 B
Plaintext
23 lines
317 B
Plaintext
ram block \RAM_BLOCK_SDP_1CLK {
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cost 64;
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abits 10;
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widths 1 2 4 8 16 per_port;
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init any;
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port sw "W" {
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clock anyedge "C";
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ifdef TRANS_OLD {
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option "TRANS" 0 {
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wrtrans "R" old;
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}
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}
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ifdef TRANS_NEW {
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option "TRANS" 1 {
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wrtrans "R" new;
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}
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}
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}
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port sr "R" {
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clock anyedge "C";
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}
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}
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