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17 lines
219 B
Verilog
17 lines
219 B
Verilog
/** small, meaningless design to test loading of liberty files */
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module small
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(
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input clk,
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output reg[7:0] count
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);
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initial count = 0;
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always @ (posedge clk)
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begin
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count <= count + 1'b1;
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end
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endmodule
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