yosys/tests/errors/syntax_err09.v at ec8b745929cd02710b2d6a2f995b46c64ff54b75 - mirrors/yosys - Libre-Chip.org

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Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

4 lines

42 B

Verilog

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	`module a(input wire x = 1'b0);`
	`endmodule`