mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
20 lines
456 B
Plaintext
20 lines
456 B
Plaintext
read_verilog <<EOF
|
|
module gate(input signed [2:0] a1, input signed [2:0] b1,
|
|
input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
|
|
wire signed [3:0] ab1;
|
|
assign ab1 = a1 * b1;
|
|
assign y = ab1 + a2*b2 + c + d + 1;
|
|
endmodule
|
|
EOF
|
|
prep
|
|
|
|
design -save gold
|
|
alumacc
|
|
opt_clean
|
|
select -assert-count 1 t:$macc_v2
|
|
maccmap -unmap
|
|
design -copy-from gold -as gold gate
|
|
equiv_make gold gate equiv
|
|
equiv_induct equiv
|
|
equiv_status -assert equiv
|