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https://github.com/YosysHQ/yosys
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9288889e20
Add simulation models, techmap, and dfflegalize rules for Gowin DL-series latch primitives. Latches use the same physical BEL as DFFs with REGMODE set to LATCH. All 12 variants are supported: DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
37 lines
1.2 KiB
Verilog
37 lines
1.2 KiB
Verilog
`default_nettype none
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// DL D Latch with Positive Gate
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module \$_DLATCH_P_ (input E, D, output Q);
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DL _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DLN D Latch with Negative Gate
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module \$_DLATCH_N_ (input E, D, output Q);
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DLN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DLC D Latch with Positive Gate and Asynchronous Clear
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module \$_DLATCH_PP0_ (input E, R, D, output Q);
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DLC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DLNC D Latch with Negative Gate and Asynchronous Clear
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module \$_DLATCH_NP0_ (input E, R, D, output Q);
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DLNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .CLEAR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DLP D Latch with Positive Gate and Asynchronous Preset
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module \$_DLATCH_PP1_ (input E, R, D, output Q);
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DLP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DLNP D Latch with Negative Gate and Asynchronous Preset
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module \$_DLATCH_NP1_ (input E, R, D, output Q);
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DLNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(E), .PRESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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