yosys/tests/verilog/genvar_loop_decl_1.sv at ebe15f684f2db046e3f16f347b3956e14313c31c - mirrors/yosys - Libre-Chip.org

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Zachary Snow b2e9717419 sv: support declaration in generate for initialization

This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.

2021-08-31 12:34:55 -06:00

18 lines

354 B

Systemverilog

Raw Blame History

 `default_nettype none
 module gate(a);
 	for (genvar i = 0; i < 2; i++)
 		wire [i:0] x = '1;
 	output wire [32:0] a;
 	assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
 endmodule
 module gold(a);
 	genvar i;
 	for (i = 0; i < 2; i++)
 		wire [i:0] x = '1;
 	output wire [32:0] a;
 	assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
 endmodule