yosys/tests/verilog/for_decl_no_init.ys at ebe15f684f2db046e3f16f347b3956e14313c31c - mirrors/yosys - Libre-Chip.org

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Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.

2021-08-30 15:19:21 -06:00

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 logger -expect error "For loop variable declaration is missing initialization!" 1
 read_verilog -sv <<EOT
 module top;
     integer z;
     initial
         for (integer i; i < 10; i = i + 1)
             z = i;
 endmodule
 EOT