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https://github.com/YosysHQ/yosys
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29 lines
1.1 KiB
Verilog
29 lines
1.1 KiB
Verilog
`default_nettype none
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module module_scope_Example(o1, o2);
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parameter [31:0] v1 = 10;
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parameter [31:0] v2 = 20;
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output wire [31:0] o1, o2;
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assign module_scope_Example.o1 = module_scope_Example.v1;
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assign module_scope_Example.o2 = module_scope_Example.v2;
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endmodule
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module module_scope_ExampleLong(o1, o2);
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
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output wire [31:0] o1, o2;
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assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
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assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
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endmodule
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module module_scope_top(
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output wire [31:0] a1, a2, b1, b2, c1, c2,
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output wire [31:0] d1, d2, e1, e2, f1, f2
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);
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module_scope_Example a(a1, a2);
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module_scope_Example #(1) b(b1, b2);
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module_scope_Example #(1, 2) c(c1, c2);
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module_scope_ExampleLong d(d1, d2);
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module_scope_ExampleLong #(1) e(e1, e2);
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module_scope_ExampleLong #(1, 2) f(f1, f2);
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endmodule
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