mirror of
https://github.com/YosysHQ/yosys
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567 lines
20 KiB
Verilog
567 lines
20 KiB
Verilog
`timescale 1ns / 1ps
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module testbench;
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parameter [0:0] NEG_TRIGGER = 0;
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parameter [0:0] C_REG = 0;
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parameter [0:0] A_REG = 0;
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parameter [0:0] B_REG = 0;
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parameter [0:0] D_REG = 0;
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parameter [0:0] TOP_8x8_MULT_REG = 0;
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parameter [0:0] BOT_8x8_MULT_REG = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
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parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
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parameter [1:0] TOPOUTPUT_SELECT = 0;
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parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
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parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
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parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
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parameter [1:0] BOTOUTPUT_SELECT = 0;
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parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
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parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
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parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
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parameter [0:0] MODE_8x8 = 0;
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parameter [0:0] A_SIGNED = 0;
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parameter [0:0] B_SIGNED = 0;
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reg CLK, CE;
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reg [15:0] C, A, B, D;
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reg AHOLD, BHOLD, CHOLD, DHOLD;
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reg IRSTTOP, IRSTBOT;
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reg ORSTTOP, ORSTBOT;
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reg OLOADTOP, OLOADBOT;
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reg ADDSUBTOP, ADDSUBBOT;
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reg OHOLDTOP, OHOLDBOT;
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reg CI, ACCUMCI, SIGNEXTIN;
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output [31:0] REF_O, UUT_O;
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output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
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output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
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integer errcount = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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if (REF_O !== UUT_O) begin
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$display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
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errcount = errcount + 1;
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end
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if (REF_CO !== UUT_CO) begin
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$display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
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errcount = errcount + 1;
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end
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if (REF_ACCUMCO !== UUT_ACCUMCO) begin
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$display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
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errcount = errcount + 1;
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end
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if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
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$display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
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errcount = errcount + 1;
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end
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#3;
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end
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endtask
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initial begin
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$dumpfile("test_dsp_model.vcd");
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$dumpvars(0, testbench);
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#2;
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CLK = NEG_TRIGGER;
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CE = 1;
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{C, A, B, D} = 0;
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{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
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{OLOADTOP, OLOADBOT} = 0;
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{ADDSUBTOP, ADDSUBBOT} = 0;
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{OHOLDTOP, OHOLDBOT} = 0;
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{CI, ACCUMCI, SIGNEXTIN} = 0;
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{IRSTTOP, IRSTBOT} = ~0;
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{ORSTTOP, ORSTBOT} = ~0;
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#3;
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{IRSTTOP, IRSTBOT} = 0;
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{ORSTTOP, ORSTBOT} = 0;
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repeat (300) begin
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clkcycle;
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A = $urandom;
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B = $urandom;
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C = $urandom;
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D = $urandom;
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{AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
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{OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
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{ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
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{OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
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{CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
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{IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
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{ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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SB_MAC16 #(
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.NEG_TRIGGER (NEG_TRIGGER ),
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.C_REG (C_REG ),
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.A_REG (A_REG ),
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.B_REG (B_REG ),
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.D_REG (D_REG ),
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.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
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.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
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.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
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.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
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.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
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.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
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.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
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.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
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.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
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.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
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.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
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.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
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.MODE_8x8 (MODE_8x8 ),
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.A_SIGNED (A_SIGNED ),
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.B_SIGNED (B_SIGNED )
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) ref (
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.CLK (CLK ),
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.CE (CE ),
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.C (C ),
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.A (A ),
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.B (B ),
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.D (D ),
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.AHOLD (AHOLD ),
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.BHOLD (BHOLD ),
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.CHOLD (CHOLD ),
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.DHOLD (DHOLD ),
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.IRSTTOP (IRSTTOP ),
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.IRSTBOT (IRSTBOT ),
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.ORSTTOP (ORSTTOP ),
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.ORSTBOT (ORSTBOT ),
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.OLOADTOP (OLOADTOP ),
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.OLOADBOT (OLOADBOT ),
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.ADDSUBTOP (ADDSUBTOP ),
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.ADDSUBBOT (ADDSUBBOT ),
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.OHOLDTOP (OHOLDTOP ),
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.OHOLDBOT (OHOLDBOT ),
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.CI (CI ),
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.ACCUMCI (ACCUMCI ),
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.SIGNEXTIN (SIGNEXTIN ),
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.O (REF_O ),
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.CO (REF_CO ),
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.ACCUMCO (REF_ACCUMCO ),
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.SIGNEXTOUT (REF_SIGNEXTOUT)
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);
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SB_MAC16_UUT #(
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.NEG_TRIGGER (NEG_TRIGGER ),
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.C_REG (C_REG ),
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.A_REG (A_REG ),
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.B_REG (B_REG ),
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.D_REG (D_REG ),
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.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
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.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
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.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
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.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
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.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
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.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
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.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
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.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
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.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
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.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
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.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
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.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
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.MODE_8x8 (MODE_8x8 ),
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.A_SIGNED (A_SIGNED ),
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.B_SIGNED (B_SIGNED )
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) uut (
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.CLK (CLK ),
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.CE (CE ),
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.C (C ),
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.A (A ),
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.B (B ),
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.D (D ),
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.AHOLD (AHOLD ),
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.BHOLD (BHOLD ),
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.CHOLD (CHOLD ),
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.DHOLD (DHOLD ),
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.IRSTTOP (IRSTTOP ),
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.IRSTBOT (IRSTBOT ),
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.ORSTTOP (ORSTTOP ),
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.ORSTBOT (ORSTBOT ),
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.OLOADTOP (OLOADTOP ),
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.OLOADBOT (OLOADBOT ),
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.ADDSUBTOP (ADDSUBTOP ),
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.ADDSUBBOT (ADDSUBBOT ),
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.OHOLDTOP (OHOLDTOP ),
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.OHOLDBOT (OHOLDBOT ),
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.CI (CI ),
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.ACCUMCI (ACCUMCI ),
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.SIGNEXTIN (SIGNEXTIN ),
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.O (UUT_O ),
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.CO (UUT_CO ),
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.ACCUMCO (UUT_ACCUMCO ),
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.SIGNEXTOUT (UUT_SIGNEXTOUT)
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);
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endmodule
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module testbench_comb_8x8_A;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_8x8_A_signedA;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_8x8_A_signedB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_comb_8x8_A_signedAB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_comb_8x8_B;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_8x8_B_signedA;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_8x8_B_signedB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_comb_8x8_B_signedAB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_comb_16x16;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_16x16_signedA;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_comb_16x16_signedB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
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.D_REG (0),
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.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_comb_16x16_signedAB;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (0),
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.A_REG (0),
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.B_REG (0),
|
|
.D_REG (0),
|
|
.TOP_8x8_MULT_REG (0),
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.BOT_8x8_MULT_REG (0),
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.PIPELINE_16x16_MULT_REG1 (0),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (1),
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.B_SIGNED (1)
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) testbench ();
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endmodule
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module testbench_seq_16x16_A;
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testbench #(
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.NEG_TRIGGER (0),
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.C_REG (1),
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.A_REG (1),
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.B_REG (1),
|
|
.D_REG (1),
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.TOP_8x8_MULT_REG (1),
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.BOT_8x8_MULT_REG (1),
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.PIPELINE_16x16_MULT_REG1 (1),
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.PIPELINE_16x16_MULT_REG2 (1),
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.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
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.A_SIGNED (0),
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.B_SIGNED (0)
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) testbench ();
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endmodule
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module testbench_seq_16x16_B;
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|
testbench #(
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|
.NEG_TRIGGER (0),
|
|
.C_REG (1),
|
|
.A_REG (1),
|
|
.B_REG (1),
|
|
.D_REG (1),
|
|
.TOP_8x8_MULT_REG (1),
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|
.BOT_8x8_MULT_REG (1),
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.PIPELINE_16x16_MULT_REG1 (1),
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.PIPELINE_16x16_MULT_REG2 (0),
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.TOPOUTPUT_SELECT (1), // 0=P, 1=Q, 2=8x8, 3=16x16
|
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.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
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.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
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.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.BOTOUTPUT_SELECT (1), // 0=R, 1=S, 2=8x8, 3=16x16
|
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.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
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.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
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.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
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.MODE_8x8 (0),
|
|
.A_SIGNED (0),
|
|
.B_SIGNED (0)
|
|
) testbench ();
|
|
endmodule
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