mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 12:28:44 +00:00
1070f2e90b
Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
30 lines
341 B
Verilog
30 lines
341 B
Verilog
module tristate (en, i, o);
|
|
input en;
|
|
input i;
|
|
output reg o;
|
|
`ifndef BUG
|
|
|
|
always @(en or i)
|
|
o <= (en)? i : 1'bZ;
|
|
`else
|
|
|
|
always @(en or i)
|
|
o <= (en)? ~i : 1'bZ;
|
|
`endif
|
|
endmodule
|
|
|
|
|
|
module top (
|
|
input en,
|
|
input a,
|
|
output b
|
|
);
|
|
|
|
tristate u_tri (
|
|
.en (en ),
|
|
.i (a ),
|
|
.o (b )
|
|
);
|
|
|
|
endmodule
|