3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-10 19:27:07 +00:00
yosys/frontends/verilog
Clifford Wolf eb452ffb28 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-23 10:32:54 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Added -no_dump_ptr flag for AST dump options in 'read_verilog' 2018-08-23 15:26:02 +03:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l Add "make coverage" 2018-08-27 14:22:21 +02:00
verilog_parser.y Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 2018-09-23 10:32:54 +02:00