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Code Activity
yosys/techlibs
History
Clifford Wolf c5b204d8d2 Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
..
altera_intel Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
common Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
coolrunner2 coolrunner2: Finish fixing special-use p-terms 2017-09-01 07:22:16 -07:00
easic Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
gowin Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
greenpak4 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
ice40 Fix synth_ice40 doc regarding -top default 2017-09-29 17:52:57 +02:00
xilinx Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00