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yosys/techlibs
Eddie Hung 9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
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achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic make note that it is for latch mode 2019-09-18 17:48:16 +02:00
common Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
coolrunner2 Fix spacing 2019-08-06 16:47:55 -07:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
efinix better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
gowin Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
intel techlibs/intel: Clean up Makefile 2019-08-05 11:22:11 -07:00
sf2 Add link to SF2 / igloo2 macro library guide 2019-03-07 09:08:26 -08:00
xilinx Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 2019-10-08 10:53:38 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00