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Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. |
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| .. | ||
| aiger | ||
| ast | ||
| blif | ||
| ilang | ||
| json | ||
| liberty | ||
| rpc | ||
| verific | ||
| verilog | ||