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yosys/frontends
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
..
aiger Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
ast Use "(id)" instead of "id" for types as temporary hack 2019-10-14 05:24:31 +02:00
blif Fix parsing of .cname BLIF statements 2019-10-16 09:06:57 +02:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
rpc Fixes for MSVC build 2019-10-04 16:29:46 +02:00
verific Add Verific support for SVA nexttime properties 2019-11-22 16:11:56 +01:00
verilog kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 2019-12-04 11:59:36 +00:00