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yosys/frontends
2025-07-09 15:58:35 +02:00
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aiger
aiger2
ast
blif
json
liberty
rpc
rtlil
verific verificsva: check -L value is small enough for code to work 2025-07-09 15:58:35 +02:00
verilog verilog: add support for SystemVerilog string literals. 2025-07-03 20:51:12 -06:00