mirror of
https://github.com/YosysHQ/yosys
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104 lines
3 KiB
Text
104 lines
3 KiB
Text
# Automatic reg as intermediate value in always @(*)
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# The result must be provably equivalent to the direct expression.
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# No latch or DFF must be created for tmp.
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design -reset
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read_verilog -sv <<EOF
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module t1(input a, b, c, output reg y);
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always @(*) begin : blk
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automatic reg tmp;
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tmp = a ^ b;
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if (c) tmp = tmp & a;
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y = tmp;
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end
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// equivalent to: y = c ? ((a^b)&a) : (a^b)
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assert property (y === (c ? ((a ^ b) & a) : (a ^ b)));
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endmodule
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EOF
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proc
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async2sync
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# no state elements for tmp
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select -assert-none t:$dff t:$dlatch %%
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sat -verify -prove-asserts -show-all
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# automatic logic in always_comb with chained computation
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# Two automatic intermediates used in sequence; result must match
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# the direct expression. No latch/DFF.
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design -reset
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read_verilog -sv <<EOF
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module t2(input [3:0] a, b, input sel, output reg [3:0] y, output reg co);
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always_comb begin : blk
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automatic reg [4:0] sum;
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automatic reg [3:0] pick;
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sum = {1'b0, a} + {1'b0, b};
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pick = sel ? sum[3:0] : (a & b);
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y = pick;
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co = sum[4];
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end
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assert property (y === (sel ? ((a + b) & 4'hf) : (a & b)));
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assert property (co === (((5'(a) + 5'(b)) >> 4) & 1'b1));
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endmodule
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EOF
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proc
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async2sync
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select -assert-none t:$dff t:$dlatch %%
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sat -verify -prove-asserts -show-all
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# automatic in a clocked block — only the explicitly registered
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# output (result) must get a DFF; the automatic temp must not.
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design -reset
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read_verilog -sv <<EOF
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module t3(input clk, rst, input [7:0] data, output reg [7:0] result);
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always @(posedge clk) begin : compute
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automatic reg [7:0] tmp;
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tmp = data ^ 8'hA5;
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if (rst)
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result <= 8'h00;
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else
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result <= tmp;
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end
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endmodule
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EOF
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proc
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# Exactly one DFF (for result), zero latches, no DFF for tmp
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select -assert-count 1 t:$dff %%
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select -assert-none t:$dlatch %%
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# automatic integer in named block — ensure integer-width
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# automatic variables work and produce no state elements.
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design -reset
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read_verilog -sv <<EOF
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module t4(input [7:0] a, b, input sub, output reg [7:0] y);
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always @(*) begin : arith
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automatic integer acc;
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if (sub)
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acc = $signed(a) - $signed(b);
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else
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acc = $signed(a) + $signed(b);
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y = acc[7:0];
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end
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assert property (y === (sub ? (a - b) : (a + b)));
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endmodule
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EOF
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proc
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async2sync
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select -assert-none t:$dff t:$dlatch %%
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sat -verify -prove-asserts -show-all
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# automatic variable not assigned on all paths (X semantics)
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# With 'automatic', tmp holds no previous state; the undriven path
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# produces X, not the old register value. After proc, no latch may be
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# inferred for tmp.
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design -reset
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read_verilog -sv <<EOF
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module t5(input en, d, output reg q);
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always @(*) begin : blk
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automatic reg tmp;
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if (en) tmp = d;
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// tmp is X when en==0: automatic means no state retention
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q = tmp;
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end
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endmodule
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EOF
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proc
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# No latch for tmp — X propagates instead of old value
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select -assert-none t:$dff t:$dlatch %%
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