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Implement iterative queue-based traversal in wreduce pass to propagate width reductions across dependent cells and wires. Previously, wreduce would process all cells once, then all wires once. This meant that reductions couldn't propagate through chains of operations. The new algorithm maintains work queues for both cells and wires, processing them iteratively until no more reductions are possible. When a cell or wire is reduced, dependent cells and wires are added back to the queues for reprocessing. Add regression test to verify that width reductions propagate through a chain of operations: (a + b)[3:0] + c, ensuring the first addition is reduced from 9 bits to 4 bits.
34 lines
791 B
Text
34 lines
791 B
Text
# Ensure wreduce propagates width reductions across dependent cells.
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read_verilog <<EOT
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module top(input [7:0] a, input [7:0] b, input [3:0] c, output [3:0] y);
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wire [8:0] sum_full;
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wire [3:0] sum_trunc;
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assign sum_full = a + b;
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assign sum_trunc = sum_full[3:0];
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assign y = sum_trunc + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_expr
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opt_clean
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design -save gold
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wreduce
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opt_clean
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# After wreduce, the first add should be reduced from 9 bits to 4 bits
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select -assert-count 2 t:$add
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select -assert-count 0 t:$add r:Y_WIDTH=9 %i
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select -assert-count 2 t:$add r:Y_WIDTH=4 %i
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design -stash reduced
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design -import gold -as gold
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design -import reduced -as reduced
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miter -equiv -flatten -make_assert -make_outputs gold reduced miter
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sat -verify -prove-asserts -show-ports miter
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