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11 lines
171 B
Verilog
11 lines
171 B
Verilog
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// test cases found using vloghammer
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// https://github.com/cliffordwolf/VlogHammer
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module test01(a, y);
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input [7:0] a;
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output [3:0] y;
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assign y = ~a >> 4;
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endmodule
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