mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 03:15:50 +00:00
6c16fd760b
Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
111 lines
2.2 KiB
Text
111 lines
2.2 KiB
Text
read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b0} + 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} + 1'b1;
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endmodule
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EOT
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alumacc
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select -assert-count 1 t:$alu
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select -assert-count none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} - 1'b1;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [1:0] a, output [3:0] y);
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assign y = -{a[1], 2'b10, a[0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 1 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-count 1 t:$not
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select -assert-count none t:$alu t:$not t:* %D %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [2:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b1, a[1:0]} + {b[2], 2'b11, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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dump
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select -assert-count 2 t:$alu
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select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
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select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
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select -assert-count none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [3:0] b, output [5:0] y);
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assign y = {a[3:2], 1'b0, a[1:0]} + {b[3:2], 1'b0, b[1:0]};
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt -fine
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design -load postopt
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select -assert-count 2 t:$alu
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select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
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select -assert-count none t:$alu t:* %D
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