mirror of
https://github.com/YosysHQ/yosys
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63 lines
2.3 KiB
Verilog
63 lines
2.3 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`ifndef _NO_FFS
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// Async reset, enable.
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module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
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FFCE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
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FFCE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
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FFPE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
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FFPE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Sync reset, enable.
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module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
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FFRE_N #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
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FFRE #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
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FFSE_N #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
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FFSE #(.INIT(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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`endif
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