mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 04:49:15 +00:00
80 lines
2.9 KiB
Python
80 lines
2.9 KiB
Python
#!/usr/bin/env python3
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import sys
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sys.path.append("..")
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import gen_tests_makefile
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import argparse
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import sys
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import random
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from pathlib import Path
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def random_plus_x():
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return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^'])
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def maybe_plus_x(expr):
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if random.randint(0, 4) == 0:
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return "(%s %s)" % (expr, random_plus_x())
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else:
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return expr
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parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
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parser.add_argument('-S', '--seed', type = int, help = 'seed for PRNG')
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parser.add_argument('-c', '--count', type = int, default = 100, help = 'number of test cases to generate')
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args = parser.parse_args()
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seed = args.seed
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if seed is None:
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seed = random.randrange(sys.maxsize)
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print("opt_share PRNG seed: %d" % seed)
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random.seed(seed)
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for path in Path(".").glob("uut_*.*"):
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if path.is_file():
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path.unlink()
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for idx in range(args.count):
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with open('uut_%05d.v' % idx, 'w') as f:
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with gen_tests_makefile.redirect_stdout(f):
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print('module uut_%05d(a, b, c, s, y);' % (idx))
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op = random.choice([
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random.choice(['+', '-', '*', '/', '%']),
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random.choice(['<', '<=', '==', '!=', '===', '!==', '>=',
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'>']),
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random.choice(['<<', '>>', '<<<', '>>>']),
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random.choice(['|', '&', '^', '~^', '||', '&&']),
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])
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), 8))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), 8))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), 8))
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print(' input s;')
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print(' output [%d:0] y;' % 8)
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ops1 = ['a', 'b']
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ops2 = ['a', 'c']
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random.shuffle(ops1)
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random.shuffle(ops2)
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cast1 = random.choice(['', '$signed', '$unsigned'])
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cast2 = random.choice(['', '$signed', '$unsigned'])
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print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s));' %
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(cast1, ops1[0], op, ops1[1],
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cast2, ops2[0], op, ops2[1]))
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print('endmodule')
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with open('uut_%05d.ys' % idx, 'w') as f:
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with gen_tests_makefile.redirect_stdout(f):
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print('read_verilog uut_%05d.v' % idx)
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print('proc;;')
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print('copy uut_%05d gold' % idx)
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print('rename uut_%05d gate' % idx)
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print('tee -o uut_%05d.txt opt gate' % idx)
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print('tee -o uut_%05d.txt opt_share gate' % idx)
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print('tee -o uut_%05d.txt opt_clean gate' % idx)
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print(
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'miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter'
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)
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print(
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'sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter'
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)
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gen_tests_makefile.generate(["--yosys-scripts"])
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