Eddie Hung 8474c5b366 Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)		2019-09-29 11:26:22 -07:00
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.gitignore
add_sub.v
add_sub.ys
adffs.v	Change sync controls to async.	2019-09-25 14:43:26 +03:00
adffs.ys	Change sync controls to async.	2019-09-25 14:43:26 +03:00
alu.v	Add new tests.	2019-08-30 09:45:33 +03:00
alu.ys	Add new tests.	2019-08-30 09:45:33 +03:00
counter.v	Add new tests.	2019-08-30 09:45:33 +03:00
counter.ys	Fix test for counter	2019-08-30 12:38:28 +03:00
dffs.v
dffs.ys
div_mod.v
div_mod.ys	tests: ice40: fix div_mod SB_LUT4 count	2019-09-10 08:47:16 +08:00
dpram.v	Add comments for examples from Lattice user guide	2019-08-29 10:49:46 +03:00
dpram.ys
fsm.v	Add new tests.	2019-08-30 09:45:33 +03:00
fsm.ys	Add new tests.	2019-08-30 09:45:33 +03:00
ice40_opt.ys
latches.v
latches.ys
logic.v	Add new tests.	2019-08-30 09:45:33 +03:00
logic.ys	Add new tests.	2019-08-30 09:45:33 +03:00
macc.v	Add more complicated macc testcase	2019-09-19 22:39:15 -07:00
macc.ys	Add more complicated macc testcase	2019-09-19 22:39:15 -07:00
memory.v
memory.ys
mul.v
mul.ys
mux.v
mux.ys
rom.v	Add comments for examples from Lattice user guide	2019-08-29 10:49:46 +03:00
rom.ys
run-test.sh	Change order of parameters, to work on other os	2019-09-27 11:31:55 +02:00
shifter.v	Add new tests.	2019-08-30 09:45:33 +03:00
shifter.ys	Add new tests.	2019-08-30 09:45:33 +03:00
tribuf.v
tribuf.ys