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Code Activity
yosys/techlibs/xilinx
History
Clifford Wolf b17d6531c8 Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
..
example_mojo_counter Cleanups in xilinx examples 2013-10-27 09:58:53 +01:00
example_sim_counter Fixed xilinx/example_sim_counter test bench 2013-11-24 17:55:46 +01:00
example_zed_counter [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 2013-10-27 21:48:39 +01:00
cells.v Added more generic _TECHMAP_ wire mechanism to techmap pass 2013-11-23 15:58:06 +01:00
Makefile.inc Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
synth_xilinx.cc Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00