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13 lines
287 B
Verilog
13 lines
287 B
Verilog
// ---------------------------------------
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(* abc9_box *)
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module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
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specify
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($DO => DO) = 0;
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(RAD[0] *> DO) = 141;
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(RAD[1] *> DO) = 379;
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(RAD[2] *> DO) = 275;
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(RAD[3] *> DO) = 379;
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endspecify
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endmodule
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