Eddie Hung 55dc5a4e4f abc9: fix SCC issues (#2694) ... * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review		2021-03-29 22:01:57 -07:00
..
.gitignore
abc9_map.v
abc9_model.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
abc9_unmap.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py	simcells: Fix reset polarity for $_DLATCH_???_ cells.	2020-06-30 15:32:06 +02:00
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v
simlib.v
synth.cc
techmap.v