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89 lines
2.3 KiB
Plaintext
89 lines
2.3 KiB
Plaintext
read_verilog << EOT
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module dffe_00( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_01( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_10( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_11( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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EOT
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proc
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opt
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design -save before
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#------------------------------------------------------------------------------
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# falling edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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design -load before
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clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# rising edge clock flops don't get matched on -neg
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select -module dffe_00 -assert-count 1 t:\\pdk_icg
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select -module dffe_01 -assert-count 1 t:\\pdk_icg
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# rising edge clock flops do get matched on -neg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_00 -assert-count 1 t:\$_NOT_
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select -module dffe_01 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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design -load before
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clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# No FF set sharing a (clock, clock enable) pair is large enough
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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# TODO test -tie_lo
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