mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			13 lines
		
	
	
	
		
			205 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			13 lines
		
	
	
	
		
			205 B
		
	
	
	
		
			Text
		
	
	
	
	
	
read_verilog <<EOT
 | 
						|
module top(input a, b, output c);
 | 
						|
bb #(1) bb();
 | 
						|
endmodule
 | 
						|
 | 
						|
module bb(input a, b, output c);
 | 
						|
parameter p = 0;
 | 
						|
assign c = a ^ b;
 | 
						|
endmodule
 | 
						|
EOT
 | 
						|
blackbox bb
 | 
						|
hierarchy
 | 
						|
write_xaiger /dev/null
 |