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Code Activity
yosys/techlibs
History
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
..
common Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
greenpak4 Fixed typo in greenpak4_counters.cc 2016-03-31 08:00:59 +02:00
ice40 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
xilinx Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00