| achronix | Organizing Speedster file names | 2017-11-08 20:23:55 -06:00 | 
		
			
			
			
			
				| common | Add "synth -noshare" | 2018-03-04 17:13:45 +01:00 | 
		
			
			
			
			
				| easic | Add first draft of eASIC back-end | 2017-09-29 17:53:43 +02:00 | 
		
			
			
			
			
				| gowin | Indenting fixes in gowin sim cell lib | 2016-11-08 18:54:00 +01:00 | 
		
			
			
			
			
				| ice40 | Fix port names in SB_IO_OD | 2017-12-10 15:33:38 +00:00 | 
		
			
			
			
			
				| intel | Add "dffinit -highlow" and fix synth_intel | 2018-01-09 18:42:19 +01:00 | 
		
			
			
			
			
				| xilinx | Add techlibs/xilinx/lut2lut.v | 2017-07-10 12:09:05 +02:00 | 
		
			
			
			
			
				| .gitignore | added .gitignore files | 2013-01-05 11:19:11 +01:00 |