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Code Activity
yosys/techlibs/xilinx
History
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
cells_xtra.sh Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
cells_xtra.v Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
drams.txt
drams_bb.v
drams_map.v
Makefile.inc Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
synth_xilinx.cc Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00