mirror of
https://github.com/YosysHQ/yosys
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53 lines
987 B
Text
53 lines
987 B
Text
read_verilog <<EOF
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(* blackbox *)
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(* gate_cost_equivalent=150 *)
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module macro;
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endmodule
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module branch1;
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macro inst1();
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macro inst2();
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macro inst3();
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endmodule
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module branch2;
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macro inst1();
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macro inst2();
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macro inst3();
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macro inst4();
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endmodule
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// branch3_submod on its own doesn't meet the threshold
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module branch3_submod();
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wire [2:0] y;
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wire [2:0] a;
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wire [2:0] b;
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assign y = a * b;
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endmodule
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// on the other hand four branch3_submods do
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module branch3;
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branch3_submod inst1();
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branch3_submod inst2();
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branch3_submod inst3();
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branch3_submod inst4();
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endmodule
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// wrapper should have zero cost when branch3 is marked
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// keep_hierarchy
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module branch3_wrapper;
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branch3 inst();
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endmodule
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module top;
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branch1 inst1();
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branch2 inst2();
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branch3_wrapper wrapper();
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endmodule
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EOF
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hierarchy -top top
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keep_hierarchy -min_cost 500
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select -assert-mod-count 2 A:keep_hierarchy
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select -assert-any A:keep_hierarchy branch2 %i
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select -assert-any A:keep_hierarchy branch3 %i
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