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14 lines
317 B
Verilog
14 lines
317 B
Verilog
`default_nettype none
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module nested_genblk_resolve_top;
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generate
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if (1) begin
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wire x;
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genvar i;
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for (i = 0; i < 1; i = i + 1) begin
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if (1) begin
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assign x = 1;
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end
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end
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end
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endgenerate
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endmodule
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