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https://github.com/YosysHQ/yosys
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94 lines
2.3 KiB
Text
94 lines
2.3 KiB
Text
verific -sv <<EOF
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module top(clk);
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input wire clk;
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parameter DEPTH_LOG2 = 4;
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parameter DEPTH = 2**DEPTH_LOG2;
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parameter BYTEWIDTH = 8;
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parameter WIDTH = BYTEWIDTH*4;
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parameter PRIME1 = 237481091;
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parameter PRIME2 = 296851369;
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(* ram_style = "block" *)
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reg [WIDTH-1:0] mem [DEPTH-1:0];
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integer i;
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initial begin
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for (i = 0; i < DEPTH; i = i + 1) begin
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// Make up data by multiplying a large prime with the address,
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// then cropping and retaining the lower bits
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mem[i] = PRIME1 * i;
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end
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end
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reg [DEPTH_LOG2-1:0] counter = 0;
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reg done = 1'b0;
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always @(posedge clk) begin
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if (!done)
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counter = counter + 1'b1;
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if (counter == 0)
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done = 1'b1;
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end
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wire [WIDTH-1:0] old_data = PRIME1 * counter;
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wire [WIDTH-1:0] new_data = PRIME2 * counter;
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reg [WIDTH-1:0] expect_old_data;
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reg [WIDTH-1:0] expect_mixed_data;
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always @(posedge clk) begin
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if (!done) begin
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expect_old_data <= mem[counter];
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mem[counter][31:24] <= new_data[31:24];
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mem[counter][23:16] = new_data[23:16]; // !!! is blocking
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mem[counter][15:8] <= new_data[15:8];
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mem[counter][7:0] <= new_data[7:0];
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expect_mixed_data <= mem[counter];
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end
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end
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reg done_delay1 = 1'b1;
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reg [WIDTH-1:0] new_data_delay1 = 1'b1;
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reg [WIDTH-1:0] old_data_delay1 = 1'b1;
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always @(posedge clk) begin
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if (!done_delay1) begin
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assert(expect_old_data == old_data_delay1);
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assert(expect_mixed_data[31:24] == old_data_delay1[31:24]);
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assert(expect_mixed_data[23:16] == new_data_delay1[23:16]);
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assert(expect_mixed_data[15:0] == old_data_delay1[15:0]);
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end
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end
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reg [DEPTH_LOG2-1:0] counter_delay1;
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always @(posedge clk) begin
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counter_delay1 <= counter;
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done_delay1 <= done;
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new_data_delay1 <= new_data;
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old_data_delay1 <= old_data;
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end
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reg [DEPTH_LOG2-1:0] counter_delay2;
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reg done_delay2 = 1'b1;
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reg [WIDTH-1:0] new_data_delay2 = 1'b1;
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always @(posedge clk) begin
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counter_delay2 <= counter_delay1;
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done_delay2 <= done_delay1;
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new_data_delay2 <= new_data_delay1;
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end
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always @(posedge clk) begin
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if (!done_delay2)
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assert(mem[counter_delay2] == new_data_delay2);
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end
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_clean
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memory -nomap -nordff
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select -assert-count 1 t:$mem_v2
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sim -assert -clock clk -n 20
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