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30 lines
1.1 KiB
Verilog
30 lines
1.1 KiB
Verilog
module top(...);
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parameter LUT_WIDTH = 4; // Multiples of 2 only
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input [LUT_WIDTH-1:0] a;
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output o1_1 = {(LUT_WIDTH/2){2'b10}} <= a;
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output o1_2 = {(LUT_WIDTH/2){2'b10}} < a;
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output o1_3 = {(LUT_WIDTH/2){2'b10}} >= a;
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output o1_4 = {(LUT_WIDTH/2){2'b10}} > a;
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output o1_5 = {(LUT_WIDTH/2){2'b10}} == a;
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output o1_6 = {(LUT_WIDTH/2){2'b10}} != a;
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output o2_1 = a <= {(LUT_WIDTH/2){2'b10}};
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output o2_2 = a < {(LUT_WIDTH/2){2'b10}};
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output o2_3 = a >= {(LUT_WIDTH/2){2'b10}};
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output o2_4 = a > {(LUT_WIDTH/2){2'b10}};
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output o2_5 = a == {(LUT_WIDTH/2){2'b10}};
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output o2_6 = a != {(LUT_WIDTH/2){2'b10}};
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output o3_1 = {(LUT_WIDTH/2){2'sb01}} <= $signed(a);
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output o3_2 = {(LUT_WIDTH/2){2'sb01}} < $signed(a);
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output o3_3 = {(LUT_WIDTH/2){2'sb01}} >= $signed(a);
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output o3_4 = {(LUT_WIDTH/2){2'sb01}} > $signed(a);
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output o3_5 = {(LUT_WIDTH/2){2'sb01}} == $signed(a);
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output o3_6 = {(LUT_WIDTH/2){2'sb01}} != $signed(a);
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output o4_1 = $signed(a) <= {LUT_WIDTH{1'sb0}};
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output o4_2 = $signed(a) < {LUT_WIDTH{1'sb0}};
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output o4_3 = $signed(a) >= {LUT_WIDTH{1'sb0}};
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output o4_4 = $signed(a) > {LUT_WIDTH{1'sb0}};
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endmodule
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