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79 lines
1.6 KiB
Verilog
79 lines
1.6 KiB
Verilog
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module mul_plain(a, b, p);
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parameter M = 6;
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parameter N = 6;
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input wire [M-1:0] a;
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input wire [N-1:0] b;
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output wire [M+N-1:0] p;
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assign p = a * b;
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endmodule
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module mul_signed_async (clk, rst, en, a, b, p);
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parameter M = 8;
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parameter N = 6;
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input wire signed clk, rst, en;
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input wire signed [M-1:0] a;
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input wire signed [N-1:0] b;
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output reg signed [M+N-1:0] p;
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reg signed [M-1:0] a_reg;
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reg signed [N-1:0] b_reg;
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// signed M*N multiplier with
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// - input and output pipeline registers
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// - asynchronous reset (active high)
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// - clock enable (active high)
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always @(posedge clk or posedge rst)
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begin
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if (rst) begin
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a_reg <= 0;
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b_reg <= 0;
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p <= 0;
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end
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else if (en) begin
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a_reg <= a;
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b_reg <= b;
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p <= a_reg * b_reg;
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end
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end
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endmodule
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module mul_unsigned_sync (clk, rst, en, a, b, p);
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parameter M = 6;
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parameter N = 3;
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input wire clk, rst, en;
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input wire [M-1:0] a;
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input wire [N-1:0] b;
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output reg [M+N-1:0] p;
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reg [M-1:0] a_reg;
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reg [N-1:0] b_reg;
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// unsigned M*N multiplier with
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// - input and output pipeline registers
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// - synchronous reset (active high)
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// - clock enable (active high)
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always @(posedge clk)
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begin
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if (rst) begin
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a_reg <= 0;
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b_reg <= 0;
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p <= 0;
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end
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else if (en) begin
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a_reg <= a;
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b_reg <= b;
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p <= a_reg * b_reg;
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end
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end
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endmodule
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